![]() ![]() parameter declaration becomes local in quad_sdi_k7gtx with formal parameter declaration list Generics, Parameters : Īnalyzing Verilog file "C:\FPGA\XAPP1169_Release\XAPP1169_Release_TX\sources\LogiCores\SMPTE2022_5_6_TX\COMMON\SDI_RXTX\verilog\dru\dru_maskencoder.v" into library workĪnalyzing Verilog file "C:\FPGA\XAPP1169_Release\XAPP1169_Release_TX\sources\LogiCores\SMPTE2022_5_6_TX\COMMON\SDI_RXTX\verilog\dru\dru_control.v" into library workĪnalyzing Verilog file "C:\FPGA\XAPP1169_Release\XAPP1169_Release_TX\sources\LogiCores\SMPTE2022_5_6_TX\COMMON\SDI_RXTX\verilog\dru\dru_rot20.v" into library workĪnalyzing Verilog file "C:\FPGA\XAPP1169_Release\XAPP1169_Release_TX\sources\LogiCores\SMPTE2022_5_6_TX\COMMON\SDI_RXTX\verilog\dru\dru_bshift10to10.v" into library workĪnalyzing Verilog file "C:\FPGA\XAPP1169_Release\XAPP1169_Release_TX\sources\LogiCores\SMPTE2022_5_6_TX\COMMON\SDI_RXTX\verilog\dru\dru.v" into library workĪnalyzing Verilog file "C:\FPGA\XAPP1169_Release\XAPP1169_Release_TX\sources\LogiCores\SMPTE2022_5_6_TX\COMMON\SDI_RXTX\verilog\fmc_code\Si5324_fsel_lookup.v" into library workĪnalyzing Verilog file "C:\FPGA\XAPP1169_Release\XAPP1169_Release_TX\sources\LogiCores\SMPTE2022_5_6_TX\COMMON\SDI_RXTX\KC705Pblaze\lmh0387t.v" into library workĪnalyzing Verilog file "C:\FPGA\XAPP1169_Release\XAPP1169_Release_TX\sources\LogiCores\SMPTE2022_5_6_TX\COMMON\SDI_RXTX\KC705Pblaze\LMH0387_control.v" into library workĪnalyzing Verilog file "C:\FPGA\XAPP1169_Release\XAPP1169_Release_TX\sources\LogiCores\SMPTE2022_5_6_TX\COMMON\SDI_RXTX\KC705Pblaze\KCSi5324.v" into library workĪnalyzing Verilog file "C:\FPGA\XAPP1169_Release\XAPP1169_Release_TX\sources\LogiCores\SMPTE2022_5_6_TX\COMMON\SDI_RXTX\KC705Pblaze\kc705_Si5324_control.v" into library workĪnalyzing Verilog file "C:\FPGA\XAPP1169_Release\XAPP1169_Release_TX\sources\LogiCores\SMPTE2022_5_6_TX\COMMON\SDI_RXTX\verilog\quad_sdi_k7gtx_drp_gt.v" into library workĪnalyzing Verilog file "C:\FPGA\XAPP1169_Release\XAPP1169_Release_TX\sources\LogiCores\SMPTE2022_5_6_TX\COMMON\SDI_RXTX\verilog\quad_sdi_k7gtx_drp.v" into library work Total CPU time to Xst completion: 0.55 secsĨ.4.2) Asynchronous Control Signals Information ![]() Total CPU time to Xst completion: 0.54 secs Total REAL time to Xst completion: 0.00 secs ![]() Then it gives the error what I posted above.Ĭopyright (c) 1995-2012 Xilinx, Inc. It didn't run then I changed the directoty to XST/ISE subdirectory of Implementation directory and try to run part by part of the buildfpga.sh content. Therefore I opened ISE command prompt, gave the path to implemention directory mentioned and then try to run buildfpga.sh shell script file. ISE directory I mean above is this one and not ISE install directory of Xilinx ISE. In implementation directory there are another 2 subdirectory with name XST and ISE apart from buildfpga.sh file. The contents of the buildfpga.sh is What I posted above as code. The script must be run from that directory. Run the buildfpga.sh shell script (found under implementation/) to generate the programming files. In page 11 of the document I linked, it is mentioned under building hardware section that: Although ISE 14.2 is mentioned in the the document I have linked but in readme.txt file (See attachment above which comes with reference design) mentioned it is build with ISE 14.5. ![]()
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